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LCX037BLT 3.4cm (1.35 type) black-and-white lcd panel description the LCX037BLT is a 3.4cm diagonal active matrix tft-lcd panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. use of three LCX037BLT panels provides a full-color representation. the striped arrangement suitable for data display is capable of displaying fine text and vertical lines. the adoption of a new developed dot-line inverse drive system, cmp (chemical mechanical polish) and ocs (on chip spacer) structures contribute to high picture quality. this panel has a polysilicon tft high-speed scanner and built-in function to display images up/down and/or right/left inverse. the built-in 5v interface circuit leads to lower voltage of timing and control signals. features number of active dots: 1,049,088 (1.35 type, 3.4cm in diagonal) high optical transmittance: 16% (typ.) dot-line inverse drive circuit ocs structure cmp (chemical mechanical polish) structure high contrast ratio with normally white mode: 300 (typ.) built-in h and v drivers (built-in input level conversion circuit, 5v driving possible) up/down and/or right/left inverse display function antidust glass package element structure dots: 1366 (h) 768 (v) = 1,049,088 built-in peripheral driver using polycrystalline silicon super thin film transistors applications liquid crystal data projectors liquid crystal multimedia projectors liquid crystal rear-projector tvs, etc. ?1 e00231a15 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ? the company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
?2 LCX037BLT v shift register v shift register up/down and/or right/left inversion control circuit h shift register p shift register com pad com pad com pad com pad 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vcom sout vv dd v ss pst dwn vst vck coml v ss hck2 hck1 hst hv dd enb sig12 sig11 sig10 sig9 sig8 sig7 sig6 sig5 sig4 sig3 sig2 sig1 comr psig4 psig3 psig2 psig1 v ss g rgt input signal level shifter circuit block diagram
3 LCX037BLT absolute maximum ratings (v ss = 0v) h driver supply voltage hv dd 1.0 to +20 v v driver supply voltage vv dd 1.0 to +20 v common pad voltage com, coml, comr 1.0 to +17 v h shift register input pin voltage hst, hck1, hck2, 1.0 to +17 v rgt v shift register input pin voltage vst, vck, pst, 1.0 to +17 v enb, dwn video signal input pin voltage sig1 to 12, psig1 to 4 1.0 to +15 v operating temperature ? topr 10 to +70 c storage temperature tstg 30 to +85 c ? panel temperature inside the antidust glass operating conditions (v ss = 0v) supply voltage hv dd 15.5 0.3v vv dd 15.5 0.3v input pulse voltage (vp-p of all input pins except video signal and uniformity improvement signal) vin 5.0 0.5v
4 LCX037BLT pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 v ss g psig1 psig2 psig3 psig4 comr sig1 sig2 sig3 sig4 sig5 sig6 sig7 sig8 sig9 sig10 sig11 sig12 hv dd rgt hst hck1 hck2 v ss coml enb vck vst dwn pst v ss vv dd sout vcom symbol description gnd for v gate uniformity improvement signal (for black) uniformity improvement signal (for black) uniformity improvement signal (for gray) uniformity improvement signal (for gray) voltage for right cs (storage capacity) electrode line video signal 1 to panel video signal 2 to panel video signal 3 to panel video signal 4 to panel video signal 5 to panel video signal 6 to panel video signal 7 to panel video signal 8 to panel video signal 9 to panel video signal 10 to panel video signal 11 to panel video signal 12 to panel power supply for h driver drive direction pulse for h shift register (h: normal, l: reverse) start pulse for h shift register drive clock pulse for h shift register drive 1 clock pulse for h shift register drive 2 gnd (h, v, drivers) voltage for left cs (storage capacity) electrode line enable pulse for gate selection clock pulse for v shift register drive start pulse for v shift register drive drive direction pulse for v shift register (h: normal, l: reverse) start pulse for p shift register drive gnd (h, v, p drivers) power supply for v, p drivers test pin; leave this pin open. common voltage of panel pin description
5 LCX037BLT input equivalent circuit to prevent static charges, protective diodes are provided for each pin except the power supplies. in addition, protective resistors are added to all pins except the video signal inputs. all pins are connected to v ss with a high resistor of 1m ? (typ.). the equivalent circuit of each input pin is shown below: (resistance value: typ.) input lc level conversion circuit (single-phase input) 2.5k ? 2.5k ? vv dd input level conversion circuit (single-phase input) 250 ? 250 ? hv dd input level conversion circuit (single-phase input) 2.5k ? 2.5k ? hv dd input hv dd 250 ? 250 ? 250 ? 250 ? level conversion circuit (2-phase input) input hv dd signal line (1) vsig1 to vsig12, psig (2) hck1, hck2 (3) rgt (4) hst (5) pst, vck (6) vst, enb, dwn (7) vcom, coml, comr 1m ? input 1m ? 1m ? 1m ? level conversion circuit (single-phase input) 250 ? 250 ? vv dd input 1m ? 1m ? 1m ? vv dd 1m ? input 1m ? (8) hv dd , v ss g, vv dd are all vss. level conversion circuit (2-phase input)
6 LCX037BLT input signals 1. input signal voltage conditions (v ss = 0v) item h shift register input voltage hst, hck1, hck2, rgt (low) (high) (low) (high) vhil vhih vvil vvih vvc vsig1, 3, 5, 7, 9, 11 vsig2, 4, 6, 8 vcom vpsig1, 2 vpsig3, 4 0.5 4.5 0.5 4.5 7.4 vvc 4.4 vvc 4.4 vvc 0.8 vvc 4.4 vvc 2.3 0.0 5.0 0.0 5.0 7.5 vvc 4.5 vvc 4.5 vvc 0.7 vvc 4.5 vvc 2.5 0.4 5.5 0.4 5.5 7.6 vvc 4.6 vvc 4.6 vvc 0.6 vvc 4.6 vvc 2.7 v v v v v v v v v v v shift register input voltage vb1, vb2, blk, vst, vck, pcg, enb, dwn video signal center voltage video signal input range ? 1 common voltage of panel ? 2 uniformity improvement signal input voltage ? 3 symbol min. typ. max. unit ? 1 input video signal shall be symmetrical to vvc. ? 2 the typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. in this case, use the voltage of which has maximum contrast as typical value. when the typical value is lowered, the maximum and minimum values may lower.
7 LCX037BLT level conversion circuit the LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. the input signal level increases to hv dd or vv dd . the v cc of external ics are applicable to 5 0.5v. sig-center vsig1, 3, 5, 7, 9, 11 time sig1, 3, 5, 7, 9, 11 sig-center vpsig1, 4 time psig4 sig-center vsig2, 4, 6, 8, 10, 12 time sig2, 4, 6, 8, 10, 12 sig-center vpsig2, 3 time psig1 psig4 psig1 psig2 psig3 psig2 psig3 h effective period h blanking period phase relationship between video signal and uniformity improvement signal ? 3 input video signal, and a uniformity improvement signal as shown phase like below. and the rise time trpsig and the fall time tfpsig of psig1 to 4 are suppressed within 400ns.
8 LCX037BLT 2. clock timing conditions (ta = 25 c) (fhckn = 6.67mhz, fvck = 25.6khz, fv = 60hz) ? 4 hckn means hck1 and hck2. ? 5 the minimum value of tdenb is 800ns. when h-blk has a long period and has some time to spare, take more time prior to other value. hst rise time hst fall time hst data set-up time hst data hold time hckn rise time ? 4 hckn fall time ? 4 hck1 fall to hck2 rise time hck1 rise to hck2 fall time vst rise time vst fall time vst data set-up time vst data hold time vck rise time vck fall time enb rise time enb fall time horizontal video period completed to enb fall time enb width vck rise/fall to enb rise time enb rise to pst rise time pst rise time pst fall time pst data set-up time pst data hold time pst rise to hst rise time trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trvst tfvst tdvst thvst trvck tfvck trenb tfenb tdenb twenb toenb topst trpst tfpst tdpst thpst tohst 10 65 15 15 5 5 800 ? 5 900 300 390 10 65 0 75 0 0 10 10 1000 1000 400 400 0 75 4 30 30 10 85 30 30 15 15 100 100 15 15 100 100 100 100 1200 1100 500 410 30 30 10 85 ns s ns item symbol min. typ. max. unit hst hck vst vck enb pst 4 cycles of hck
9 LCX037BLT ? 6 definitions: the right-pointing arrow ( ) means +. the left-pointing arrow ( ) means . the black dot at an arrow ( ) indicates the start of measurement. hst rise time hst hck hst fall time hst data set-up time hst data hold time hckn rise time ? 4 hckn fall time ? 4 hck1 fall to hck2 rise time hck1 rise to hck2 fall time hckn ? 4 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn ? 4 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn ? 4 duty cycle 50% to1hck = 0ns to2hck = 0ns trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck item symbol waveform conditions 90% 10% 10% 90% hst trhst tfhst 50% 50% ? 6 hst hck1 tdhst thhst 50% 50% ? 4 hckn 10% 10% 90% 90% trhckn tfhckn 50% 50% ? 6 hck1 to2hck to1hck 50% 50% hck2
10 LCX037BLT vck vck rise time vck fall time trvck tfvck item symbol waveform conditions vck 10% 10% 90% 90% trvckn tfvckn vst rise time vst vst fall time vst data set-up time vst data hold time trvst tfvst tdvst thvst 90% 10% 10% 90% vst trvst tfvst 50% 50% ? 6 vst vck tdvst thvst 50% 50% enb enb rise time enb fall time horizontal video period completed to enb fall time trenb tfenb tdenb enb width vck rise/fall to enb fall time twenb toenb enb rise to pst rise time topst 90% 90% 10% 10% tfenb trenb enb h blanking period h video period 50% 50% 50% 50% twenb toenb topst tdenb enb vck pst ? 6
11 LCX037BLT item symbol waveform conditions pst 50% hst hckn 50% topst ? 6 1234 50% 50% pst hckn tdpst thpst 50% 50% pst pst rise time trpst pst fall time tfpst pst data set-up time tdpst pst data set-up time pst rise to hst rise time thpst tohst 90% 10% 10% 90% pst trpst tfpst
12 LCX037BLT electrical characteristics (ta = 25 c, hv dd = 15.5v, vv dd = 15.5v) 1. horizontal drivers item input pin capacitance hckn hst input pin current hck1 hck2 hst rgt video signal input pin capacitance current consumption chckn chst csig ih hck1 = gnd hck2 = gnd hst = gnd rgt = gnd hckn: hck1, hck2 (6.67mhz) 1000 1000 500 150 15 15 500 500 170 40 180 15 20 20 250 25 pf pf a a a a pf ma symbol min. typ. max. unit condition 2. vertical drivers item input pin capacitance vck vst, pst input pin current vck, pst vst, enb, dwn current consumption cvck cvst iv 500 150 15 15 150 35 20 20 20 30 pf pf a a ma symbol min. typ. max. unit condition 3. total power consumption of the panel 4. pin input resistance item pin v ss input resistance rpin 0.4 1 m ? symbol min. typ. max. unit item total power consumption of the panel pwr 550 1000 mw symbol min. typ. max. unit vck = gnd, pst = gnd vst, enb, dwn = gnd vck: (25.6khz) 5. uniformity improvement signal item input pin capacitance for uniformity improvement signal cpsig1 to 4 0.5 nf symbol min. typ. max. unit 5.0
13 LCX037BLT reflection preventive processing when a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. this prevents characteristic deterioration caused by luminous reflection. electro-optical characteristics item contrast ratio 25 c 25 c 25 c 60 c 25 c 60 c 25 c 60 c 0 c 25 c 0 c 25 c 60 c 25 c 25 c cr t rv 90-25 gv 90-25 bv 90-25 rv 90-60 gv 90-60 bv 90-60 rv 50-25 gv 50-25 bv 50-25 rv 50-60 gv 50-60 bv 50-60 rv 10-25 gv 10-25 bv 10-25 rv 10-60 gv 10-60 bv 10-60 ton0 ton25 toff0 toff25 f yt60 ctk 200 13 0.9 1.0 1.2 0.9 1.0 1.1 1.3 1.4 1.5 1.2 1.3 1.4 1.7 1.8 1.9 1.7 1.8 1.8 300 16 1.3 1.4 1.6 1.3 1.4 1.5 1.7 1.8 1.9 1.6 1.7 1.8 2.1 2.2 2.3 2.1 2.2 2.2 24.0 9.0 99.0 27.0 82.0 0 1.6 1.7 1.9 1.6 1.7 1.8 2.0 2.1 2.2 1.9 2.0 2.1 2.4 2.5 2.6 2.4 2.5 2.5 80.0 40.0 200.0 70.0 40.0 5 1 2 3 4 5 6 7 % v ms db s % optical transmittance v-t characteristics v 90 v 50 on time off time v 10 response time flicker image retention time cross talk symbol measurement method min. typ. max. unit
14 LCX037BLT

measurement system i measurement system ii luminance meter measurement equipment light detector measurement equipment screen: made by sony (vps-120fh: gain 2.8, glass beaded type) or equivalent projection lens: focal distance 80mm, f1.9 light source: 155w metal haloid arc lamp (color temperature 7500k 500) ( 24, sensor area: 7mm ) polarizer: side of incidence-nitto denko s eg-1224du or polatechno s skn-18242t side of output light-polatechno's shc-128 or equivalent optical fiber lcd panel light receptor lens drive circuit light source basic measurement conditions (1) driving voltage hv dd = 15.5v, vv dd = 15.5v vvc = 7.5v, vcom = 6.8v (2) measurement temperature 25 c unless otherwise specified. (3) measurement point one point in the center of the screen unless otherwise specified. (4) measurement systems two types of measurement systems are used as shown below. (5) video input signal voltage (vsig) vsig = 7.5 v ac [v] (v ac = signal amplitude) screen lcd projector approx. 2000mm 1. contrast ratio contrast ratio (cr) is given by the following formula (1). cr = l (white) ... (1) l (black) l (white): surface luminance of the center of the screen at the input signal amplitude v ac = 0.5v. l (black): surface luminance of the center of the screen at v ac = 5.5v. both luminosities are measured by system i .
15 LCX037BLT 2. optical transmittance optical transmittance (t) is given by the following formula (2). white luminance t = 100 [%] ... (2) luminance of light source "white luminance" means the maximum luminance on the screen at the input signal amplitude v ac = 0.5v on measurement system i . 3. v-t characteristics v-t characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by system ii by inputting the same signal amplitude v ac to each input pin. v 90 , v 50 , and v 10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 4. response time response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 ton ...(5) toff = t2 toff ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. the relationships between t1, t2, ton and toff are shown in the right figure. 90 50 10 v 90 v 50 v 10 v ac signal amplitude [v] transmittance [%] input signal voltage (waveform applied to the measured pixels) 4.5v 0.5v 7.0v 0v optical transmittance output waveform 100% 90% 10% 0% ton t1 ton toff t2 toff
16 LCX037BLT 5. flicker flicker (f) is given by formula (7). dc and ac (sxga: 30hz, rms) components of the panel output signal for gray raster ? mode are measured by a dc voltmeter and a spectrum analyzer in system ii . f [db] = 20log { ac component } ...(7) dc component 6. image retention time apply the monoscope signal to the lcd panel for 60 minutes and then change this signal to the gray scale of vsig = 7.5 v ac (v ac : 3 to 4v). judging by sight at the v ac that holds the maximum image retention, measure the time till the residual image becomes indistinct. ? monoscope signal conditions: vsig = 7.5 4.5 or 2.0 [v] (shown in the right figure) vcom = 6.8v 7. cross talk cross talk is determined by the luminance differences between adjacent areas represented by wi' and wi (i = 1 to 4) around a black window (vsig = 4.5 v/1v). cross talk value ctk = 100 [%] ? each input signal voltage for gray raster mode is given by vsig = 7.0 v 50 [v] where: v 50 is the signal amplitude which gives 50% of transmittance in v-t characteristics. black level white level vsig waveform 7.5v 0v 5.5v 2.0v 5.5v 2.0v w1 w1 ' w3 w3 ' w2 w2 ' w4 ' w4 wi' wi wi
17 LCX037BLT viewing angle characteristics (typical value) 90 270 180 0 theta phi 70 50 100 150 200 250 aa aa 50 aa aa 20 aa aa 10 cr = 5 10 30 180 x 270 y 0 90 z 0 marking measurement method
18 LCX037BLT optical transmittance of lcd panel (typical value) 30 20 10 0 400 500 600 700 wavelength [nm] trans. [%] measurement method: measurement system ii
19 LCX037BLT 1. dot arrangement the dots are arranged in a stripe. the shaded area is used for the dark border around the display. (tft substrate view from com pad) 6 dots 2 dots 768 dots gate sw gate sw gate sw gate sw gate sw gate sw 2 dots 6 dots 6 dots 6 dots 1 dots 1 dot 1366 dots video 1 2 3 4 5 6 1 2 3 4 5 6 gate: 1st gate: 2nd gate: 767th gate: 768th 111 1 22 2 2 1111 222 767 767 767 767 767 767 767 767 photo-shielding gate: d1st 1 1 2 active area d1 d1 d1 d1 d1 d1 d1 d1 d1 768 768 767 768 768 768 768 768 767 768 (upper) (lower) (left) (right) 1 2 767 down scan: for video , , , input signal prior one line from video , , . up scan: for video , , , input signal prior one line from video , , . 1 2 3 4 5 6 1 2 3 4 5 6 : pixel of transistor open and close at the d1st gate : pixel of transistor open and close at the 1st gate : pixel of transistor open and close at the 2nd gate : : pixel of transistor open and close at the 767th gate d1
20 LCX037BLT 2. lcd panel operations [description of basic operations] to perform dot-line inverse drive, the pixel arrangement of the same gate is as shown in the diagram. therefore, the input signal matched to respective orrangement is requied for input signals sig1 to 12. a vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 768 gate lines sequentially in a single horizontal scanning period. a horizontal driver, which consists of horizontal shift registers, gates and cmos sample-and-hold circuits, applies selected pulses to every 1366 signal electrodes sequentially in a single horizontal scanning period. these pulses are used to supply the sampled video signal to the row signal lines. vertical and horizontal shift registers address one pixel, and then thin film transistors (tfts; two tfts) turn on to apply a video signal to the dot. the same procedures lead to the entire 1366 768 dots to display a picture in a single vertical scanning period.
21 LCX037BLT this lcd panel has the following functions to easily apply to various uses, as well as various broadcasting systems. right/left inverse mode up/down inverse mode these modes are controlled by two signals (rgt and dwn). the right/left and/or up/down setting modes are shown below. right/left and/or up/down mean the direction when the pin 1 marking is located at the right side with the pin block upside. to locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for the h system must be varied. the phase relationship between the start pulse and the clock for each mode is shown below. v effective display period 768h vst vck gate name 765 766 767 768 1234 d1 4321 768 767 766 765 d1 v effective display period 768h vst vck gate name vertical direction display period (dwn = l) h display period 228v 226 227 228 d1 1234 hst hck1 pst 225 d2 hck2 horizontal direction display period (rgt = l) h display period 228v 32 1 d1 228 227 226 225 hst hck1 pst 4 d2 hck2 horizontal direction display period (rgt = h) vertical direction display period (dwn = h) rgt mode right scan left scan h l dwn mode down scan up scan h l
22 LCX037BLT 3. 12-dot simultaneous sampling the horizontal shift register samples signals vsig1 to vsig6, vsig7 to vsig12 simultaneously. this requires phase matching between signals vsig1 to vsig12 to prevent the horizontal resolution from deteriorating. thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the lcd panel. the block diagram of the delaying procedure using the sample-and-hold method is as follows. the following phase relationship diagram indicates the phase setting for right scan (rgt = high). for left scan (rgt = low), the phase settings for signals vsig1 to vsig12 are exactly reversed. vsig1 s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h s/h ck12 vsig2 vsig3 vsig4 vsig5 vsig6 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 7 8 9 10 11 12 13 14 LCX037BLT s/h ck11 s/h ck10 s/h ck9 s/h ck8 s/h ck7 ck6 s/h ck5 s/h ck4 s/h ck3 s/h ck2 s/h ck1 vsig1 vsig2 vsig3 vsig4 vsig5 vsig6 vsig7 vsig8 vsig9 vsig10 vsig11 vsig12 15 16 17 18
23 LCX037BLT (right scan) hckn ck1 ck2 ck3 ck4 ck5 ck6 ck7 ck8 ck9 ck10 ck11 ck12 display system block diagram an example of display system is shown below. digital signal driver cxd2467q cxd3504r r-in g-in b-in vsync hsync 16 16 16 60 60 1/2 x'tal mck cxa3197r cxa3512r cxa3197r cxa3512r cxa3197r cxa3512r cxa3197r cxa3512r cxa3197r cxa3512r cxa3197r cxa3512r lcx037 6 6 lcx037 6 6 lcx037 6 6 frp, prg, enb timing pulse selection-type delay line d/a s/h driver
24 LCX037BLT notes on handling (1) static charge prevention be sure to take the following protective measures. tft-lcd panels are easily damaged by static charges. a) use non-chargeable gloves, or simply use bare hands. b) use an earth-band when handling. c) do not touch any electrodes of a panel. d) wear non-chargeable clothes and conductive shoes. e) install conductive mats on the working floor and working table. f) keep panels away from any charged materials. g) use ionized air to discharge the panels. (2) protection from dust and dirt a) operate in a clean environment. b) when delivered, the panel surface (glass panel) is covered by a protective sheet. peel off the protective sheet carefully so as not to damage the glass panel. c) do not touch the glass panel surface. the surface is easily scratched. when cleaning, use a clean- room wiper with isopropyl alcohol. be careful not to leave a stain on the surface. d) use ionized air to blow dust off the glass panel. (3) other handling precautions a) do not twist or bend the flexible pc board especially at the connecting region because the board is easily deformed. b) do not drop the panel. c) do not twist or bend the panel or panel frame. d) keep the panel away from heat sources. e) do not dampen the panel with water or other solvents. f) avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) minimum radius of bending curvature for a flexible substrate must be 1mm. h) torque required to tighten screws on a panel must be 3kg cm or less. i) use appropriate filter to protect a panel. j) do not pressure the portion other than mounting hole (cover).
25 LCX037BLT package outline unit: mm 1 2 3 4 5 7 8 9 output light polarizing axis 42.0 0.15 (30.05) (16.90) 18.0 0.15 (62.6) 101.5 1.4 34.0 0.1 39.0 0.15 4-r2.5 17.5 0.05 4.9 0.1 thickness of the connector 0.3 0.05 2.2 0.1 2.5 0.1 21.0 0.15 6.0 0.1 30.0 0.1 incident light 3- 2.3 0.05 electrode (enlarged) pin34 pin1 p 0.5 0.02 33 = 16.5 0.03 0.5 0.1 0.5 0.15 4.0 0.3 0.35 0.03 the rotation angle of the active area relative to h and v is 1 . active area incident light polarizing axis 6 weight 13.7g description molding material outside frame reinforcing board reinforcing material f p c no 1 2 3 4 5 6 cover 1 7 8 cover 2 9 glass 1 glass 2 2.1 0.05 2.1 0.05 sony corporation

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